This invention relates to nonvolatile semiconductor memory devices, more particularly, to electrically-erasable, electrically-programmable, read-only memories (EEPROMs) of the floating-gate type and to methods for making and programming such devices.
The EEPROMs disclosed in co-pending U.S. patent applications Ser. Nos. 07/494,042; 07/494,051 and 07/494,060 provide greatly improved structures and methods for making nonvolatile memory cells having reduced size. The memory chips using those cells require one relatively low-voltage (perhaps +5 volts) external power supply. The memory cells of those inventions use Fowler-Nordheim tunnelling for erasure and for programming.
The nonvolatile memory cell structure disclosed in U.S. patent application Ser. No. 07/494,042, filed Mar. 15, 1990, a continuation of abandoned U.S. patent application Ser. No. 07/219,529 filed July 15, 1988, describes a floating-gate cell with a split gate and with one remote Fowler-Nordheim tunnelling window. The nonvolatile memory cell structures disclosed in U.S. patent application Ser. No. 07/568,646, assigned to Texas Instruments Incorporated, include a cell structure without a split gate and having two remote Fowler-Nordheim tunnelling windows, one on the source side of each cell and the other on the drain side of each cell. The memory cell structures disclosed in U.S. patent application Ser. No. 07/374,381 and in U.S. Pat. No. 4,947,222, both of which are also assigned to Texas Instruments Incorporated, include paired cell structures with split gates, but having one Fowler-Nordheim tunnelling window and having a field-plate to provide isolation between paired cells during programming. The memory cells of the latter application and patent share common drain-column lines, reducing the number of bitlines required per column of cells from two to only one and one-half and, therefore, reducing the area requirement per cell. The channels of the cell structures described in the latter application and patent are divided into three sub-channels and the conductivities of each of the three series-connected sub-channels are individually controlled by the field-plate, the floating gate and the control gate, respectively.
In general, the tunnelling window insulators of EEPROM memory cells deteriorate after a number, perhaps tens of thousands, of program/erase cycles, the deterioration causing inability of the floating gates to be charged or erased adequately. Use of a two-tunnelling-window structure such as that of the aforementioned U.S. patent application Ser. No. 07/568,646 would provide a cell with longer life if one of the tunnelling windows of each cell could be used for programming only and the other of the tunnelling windows could be used for erasing only. However, when connected in a array of rows and columns of such cells, the programming current does not generally flow solely through one of the tunnelling windows because the channel region is conductive during programming. In addition, the lack of a split gate requires that the array must contain circuitry to prevent or remove the adverse effects of over-erased cells. There is a need for a two-tunnelling-window memory cell structure for use in an array in a manner that programming current is confined to one of the two tunnelling regions and erasing current is confined to the other and in a manner that does not require added circuitry to prevent or correct over-erased cells.